Included
● QChip FPGA IP Core (synthesizable RTL)
● AXI4-Stream data interfaces (Master and Slave)
● AXI4-Lite control interface
● Qwyit stream cipher and key exchange logic
● Register map and user documentation
● License-controlled core (evaluation and production supported)
Key Features
● Real-time stream encryption and decryption
● Implements the Qwyit PDAF_SEC cryptographic protocol
● Continuous key evolution with no repeating keystream
● No block-size or message-length restrictions
● Quantum-safe cryptographic design
● Replacement for AES stream-mode implementations
● Fully parameterized data width and FIFO depth
● Designed for low latency and high throughput
● Compatible with most modern FPGA families
Typical Applications
● Secure FPGA-based communications
● Defense and aerospace systems
● Industrial control and automation
● Secure sensor and telemetry pipelines
● Embedded and edge computing platforms
● Replacement for AES in stream cipher modes